This is a progress note. We are publishing it because it is roughly the midpoint of a research thread that has been running for several quarters, and because we think the picture has clarified enough that we can talk about it without hedging more than is honest. Project Q-Core is our quantum work. The goal is narrow: reduce the cryogenic overhead required to operate a useful quantum error-correction stack. The goal is not to build a fault-tolerant quantum computer this year, and we are not announcing that we have one. The goal is to push on a specific, identifiable bottleneck in the path to one.
Why cryogenic overhead is the bottleneck
The dominant superconducting-qubit architectures operate at temperatures in the low tens of millikelvin. Maintaining that temperature is feasible for tens, hundreds, even thousands of qubits given enough dilution-refrigerator capacity. It is increasingly painful at ten thousand and unworkable at the millions of physical qubits implied by any honest accounting of what a fault-tolerant quantum machine running practical workloads would require. The reason is not principally the qubits themselves. It is the surrounding infrastructure: the wiring that carries control signals into the cold stage, the readout amplifiers, the digital-to-analog conversion chain, the classical compute that participates in the error-correction loop. Each of those subsystems dissipates heat. Each kilowatt of dissipation at the cold stage requires kilowatts of cooling power at the warm side. The economics, the floor area, and the energy budget all bend the wrong way as the qubit count grows.
There are several reasonable bets to make against this constraint. You can move the qubit modality — trapped ions, neutral atoms, photonic qubits each have a different thermal profile. You can move the control electronics into the cold stage, which is the cryo-CMOS thread of the literature. You can make the qubits more error-tolerant per physical unit, which reduces the number of physical qubits per logical qubit and thus the total wiring burden. We are pursuing the third path, with a particular angle on the encoding.
What topological codes give you
Topological codes — surface codes, color codes, and their relatives — are the workhorse error-correction schemes of contemporary fault-tolerant proposals. They have several appealing properties. The relevant errors are local; the syndrome extraction is geometrically tractable; the codes can be planar or near-planar, which matches the fabrication realities of superconducting devices. They have well-understood thresholds — surface codes are around 1% physical error rate per gate before the logical error rate stops decreasing with code distance — and a deep theoretical literature behind them.
What topological codes do not give you is a free lunch on the decoder. The decoder is the classical-computational component that reads the syndrome measurements and infers what corrections to apply. The decoder must run inside the round of measurement; if it does not, the error rate compounds during the wait. The decoder also has to be good — better than a strict matching algorithm, because matching ignores correlations between syndromes that a real device will produce. The dominant approach for the last several years has been minimum-weight perfect matching with various correction layers; recent work has explored learned decoders, including neural-network decoders, recurrent architectures, and graph-neural-network variants.
Our specific approach
We are combining two elements. The first is a tailored topological encoding optimized for the noise profile of our target device. Standard surface codes are noise-symmetric; a real device is not, and there is meaningful headroom in choosing an encoding whose protection is biased toward the dominant error channel. This is not new in the literature — biased-noise surface codes and XZZX codes have been studied for several years — but the specific co-design with our device’s measured noise channels is, we believe, novel in its quantitative claims.
The second element is a learned decoder, trained against a high-fidelity noise simulator and refined against measured data from the device. The decoder is split: a fast, low-latency component runs at the cold stage as a small custom inference engine, handling the common cases at the round-by-round timescale; a heavier component runs at the warm side and is consulted only when the fast decoder reports low confidence. The split is the design lever. We move as much of the decoding out of the cold stage as we can without violating the round-time budget.
Latency-budget framing
The cleanest way to think about the decoder boundary is as a latency budget. A round of syndrome extraction takes roughly a microsecond on the device class we are working with. The fast decoder must produce a correction for the typical case in less time than that. The slow decoder, at the warm side, can take longer — tens to hundreds of microseconds — but must produce a result before the accumulated uncorrected error grows large enough to threaten the logical state. The budget is tight and the budget is the design constraint. Every joule we move out of the cold stage is a joule we have to pay for at the warm side, plus the latency cost of the wire crossing the temperature gradient, plus the amplification noise that crossing introduces.
Our internal numbers — which we are not publishing in detail at this point because they are device-specific and we do not yet trust the generalization — show that the split decoder approach, on our target device, reduces cold-stage power dissipation per logical qubit by a factor we consider material. The factor is more than 2x and less than 10x depending on the workload mix and the noise profile. We will publish the underlying methodology and the device-independent components of the analysis when the work is at a stage where external researchers can reproduce it.
Preliminary results
We have run the full encoder-decoder stack on a constructed noise model that we believe reflects our target device, and on a smaller subset of measured-data sequences from device runs. The qualitative findings are: the biased-noise encoding produces logical error rates lower than the symmetric baseline at equivalent code distances; the split decoder achieves the latency budget on our cold-stage inference engine; the round-time degradation under realistic correlated noise is within a factor we consider workable for near-term scaling experiments. The quantitative claims will appear in the technical writeup.
The work has been done by a small team and benefits from collaboration with two academic groups whose contributions we will acknowledge in the technical paper. We have run the work past two external reviewers who specialize in quantum error correction; their feedback shaped the noise model and the evaluation methodology, and we are grateful for it.
What we are not claiming
We are not claiming room-temperature qubits. The qubits at the heart of the system still operate at millikelvin temperatures and we expect that to remain true for the foreseeable future. The reduction we are reporting is in the cryogenic overhead — the wiring, the control, the decoder — not in the operating temperature of the qubits themselves.
We are not claiming a path to fault-tolerant quantum computation on a near-term timeline. The honest read of the field, including ours, is that fault-tolerant quantum computation at scale remains a multi-year program for any laboratory, and that the bottlenecks are distributed across qubit fabrication, control, error correction, and software. Q-Core attacks one of those bottlenecks. Closing that one does not, on its own, close the others.
We are not claiming a generic quantum advantage. The class of workloads for which a fault-tolerant quantum machine is decisively better than a classical one remains, in the practical regime, narrower than the field’s marketing sometimes suggests. Our ambitions for what Q-Core’s machine class would do, when it exists, are specific: simulation of strongly correlated quantum systems, certain optimization classes with provable quantum speedup, and cryptographic primitives. Beyond that, we suspend judgment.
What comes next
Over the next two quarters we plan to publish: a technical paper on the biased-noise encoding and its relationship to our device’s measured noise channels; the simulator we have been using for decoder training and evaluation, with the device-specific parameters abstracted; the decoder split methodology, with reproducible benchmarks on a public device emulator. We will also do a more thorough joint engagement with the cryo-CMOS community, because we believe the path forward is in the composition of the two threads, not in the substitution of one for the other.
A note on why we are publishing the progress at this midpoint rather than waiting for the technical paper. The quantum-computing field has accumulated a non-trivial credibility debt over the last decade, with announcements that did not survive third-party scrutiny and timelines that drifted further out as the work proceeded. We are not interested in adding to the debt. The honest accounting of what we have done is: we have a specific approach, we have early evidence that it does what we hoped, we have not yet run the larger-scale experiments that would let us make the strong claims, and we are several quarters from a paper that an external reader could fully evaluate. Publishing the methodology now, with the limitations stated explicitly, lets the community engage with the approach on its merits and lets us course-correct earlier if our framing is wrong. We treat this as the appropriate norm for progress notes on long-running technical projects, and we will apply it consistently across the lab.
The substantive ongoing research is at research / quantum AI. The broader research thread on classical-quantum hybrid computation is at research / cognitive computing. We will update this page as the artifacts ship.
— Rehan Temkar, Co-founder, Apik Systems